1. Field of the Invention
The present invention relates generally to the field of integrated circuits. More particularly, the present invention relates to reversible fusible link programming through utilization of phase change materials in semiconductor integrated circuits.
2. Description of the Related Art
Redundancy in integrated circuit memories is part of the current chip manufacturing strategy to improve yield. By replacing defective cells with duplicate or redundant circuits on chips, integrated circuit memory yields are significantly increased. The current practice is to blow conductive connections (fuses), thereby allowing the redundant memory cells to be used in place of non functional cells. It is also common practice to provide for customization of chips and modules to adapt chips to specific applications. By selectively blowing fuses within an integrated circuit having multiple potential uses, a single integrated circuit design may be economically manufactured and adapted to a variety of custom uses.
Current E-Fuse Technology is capable of providing hierarchal repair of the chip at multiple levels; a first repair at first pass wafer final test (WFT), a second repair at 2nd pass WFT, and a third repair during the final test of the packaged chip. To implement this hierarchal repair, either the fuses are programmed at each stage of repair, or the data is saved as strings for each level until the final level where all fuses are programmed. With the first method where the fuses are programmed at each stage of repair extra redundancy must be built in to allow this repair in three steps. This is sometimes inefficient and leads to duplicate repairs at multiple levels requiring extra redundancy. The other option, where all the fuses are programmed at once at the final test level, has the advantage of preventing unnecessary programming of fuses in level one that would require repair at a higher level, thus reducing the amount of redundancy required to achieve the same repair. However, this repair can be done only once and must incorporate all the repair data from the different levels of test, preventing any repair or tailoring at the customer or end user site.
In addition, programming currents of about 10 mA and voltages of 3.3 to 3.5 V are required. This order of current requires a wide programming transistor, consuming significant silicon area. If this current can be reduced there could be significant savings in silicon area.
Reprogrammable Fuses utilizing chalcogenide materials and indirect heating through a resistive heater are described in U.S. Pat. No. 6,448,576 B1 entitled Programmable Chalcogenide Fuse Within A Semiconductor Device of John D. Davis et al. which is assigned to BAE Systems Information and Electronic Systems Integration, Inc., the contents of which are incorporated herein by reference in their entirety.